Configuration of VLSI Arrays in the Presence of Defects
Journal of the ACM (JACM)
Reconfigurable Multipipelines for Vector Supercomputers
IEEE Transactions on Computers
Design, analysis and reconfiguration of defect-tolerant VLSI and parallel processor arrays
Design, analysis and reconfiguration of defect-tolerant VLSI and parallel processor arrays
Reconfiguration of fault tolerant VLSI systems
Reconfiguration of fault tolerant VLSI systems
Advanced Computer Architecture: Parallelism,Scalability,Programmability
Advanced Computer Architecture: Parallelism,Scalability,Programmability
| Hi-index | 14.98 |
For a reconfigurable architecture, the harvest rate is the expected percentage of defect-free processors that can be connected into the desired topology. In this paper, we give an analytical estimation for the harvest rate of reconfigurable multipipelines based on the following model: There are n pipelines each with m stages, where each stage of a pipeline is defective with identical independent probability 0.5 and spare wires are provided for reconfiguration. By formulating the "shifting" reconfiguration as weighted chains in a partial ordered set, we prove when n = 驴(m), the harvest rate is between 34% and 72%.