A General Reconfiguration Technique for Fault Tolerant Processor Architectures

Authors:
Eshwar Belani;Ravi Mittal
Affiliations:
-;-
Venue:
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Year:
1997

Citing 3
Cited 0

Interstitial Redundancy: An Area Efficient Fault Tolerance Scheme for Large Area VLSI Processor Arrays

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A Taxonomy of Reconfiguration Techniques for Fault-Tolerant Processor Arrays

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A reconfigurable and fault-tolerant VLSI multiprocessor array

ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture

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Abstract

In this paper we present a new approach for fault tolerance in VLSI processor architectures. The reconfiguration technique is a general one in the sense that it can be applied to any arbitrary architecture with any number of spares each of which may be connected to an arbitrary number of processing elements. The technique is composed of two stages, local and global reconfiguration. In the local reconfiguration stage, faulty cells are maximally mapped onto adjacent spares. In the global stage, the shortest path from a faulty cell to a spare is found and the spare is ``propagated'' to the faulty site by the logical displacement of processing elements along that path.