VLSI array processors
A Data Compression Technique for Built-In Self-Test
IEEE Transactions on Computers
Computer Architecture and Parallel Processing
Computer Architecture and Parallel Processing
A reconfigurable and fault-tolerant VLSI multiprocessor array
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Reconfiguration for fault tolerance using graph grammars
ACM Transactions on Computer Systems (TOCS)
Fault Detection in Multiprocessor Systems and Array Processors
IEEE Transactions on Computers
On the Identification of Vertices and Edges Using Cycles
AAECC-14 Proceedings of the 14th International Symposium on Applied Algebra, Algebraic Algorithms and Error-Correcting Codes
| Hi-index | 14.98 |
Proposes a new approach for identification of faulty processing elements based on an analysis of the compressed test response of the system. The test response is compressed first in space and then in time, and faulty processing elements are identified by hard decision decoding of the corresponding space-time signature. The approach results in considerable savings in hardware required for diagnostics.