An Efficient Unsorted VLSI Dictionary Machine
IEEE Transactions on Computers
Logic testing and design for testability
Logic testing and design for testability
Accumulator Compression Testing
IEEE Transactions on Computers - The MIT Press scientific computation series
A Reconfiguration Scheme for Yield Enhancement of Large Area Binary Tree Architectures
IEEE Transactions on Computers - Fault-Tolerant Computing
Analysis and Design of Linear Finite State Machines for Signature Analysis Testing
IEEE Transactions on Computers
Fast Transforms: Algorithms, Analyses, Applications
Fast Transforms: Algorithms, Analyses, Applications
Diagnosis by Signature Analysis of Test Responses
IEEE Transactions on Computers
A Novel Concurrent Error Detection Scheme for FFT Networks
IEEE Transactions on Parallel and Distributed Systems
Finite Orthogonal Series in Design of Digital Devices
Finite Orthogonal Series in Design of Digital Devices
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Off-line testing of large multiprocessor networks or VLSI chips with many outputs requires a large volume of memory for reference data storage. Space compaction combined with time compression of test responses can essentially reduce an overhead required for testing and diagnosis. In this paper, we discuss the problem of optimal design for space compressors (compactors), to minimize the number of observation points for detection of single faulty components in multiprocessor networks. A space compactor is assumed to be followed by a time compressor, to detect a fault not necessarily manifesting itself for a single test pattern.We formulate the rules of design for a space compaction matrix for the topology of the circuit-under-test (CUT) modeled by an arbitrary acyclic graph. Tree arrays and Fourier transform networks are considered as examples. The lower and upper bounds on the number of space compactor outputs are obtained, and optimal space compaction matrices are determined for above mentioned CUT topologies. Simple procedures for design of off-line testing devices with built-in self-testing are presented. Estimations on a complexity of proposed designs are given.