IEEE Transactions on Computers
A Fault-Tolerant FFT Processor
IEEE Transactions on Computers
Fault-Tolerant Matrix Triangularizations on Systolic Arrays
IEEE Transactions on Computers
Algorithm-Based Fault Detection for Signal Processing Applications
IEEE Transactions on Computers
Efficient FFT network testing and diagnosis schemes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fault Detection in Multiprocessor Systems and Array Processors
IEEE Transactions on Computers
An Efficient Algorithm-Based Concurrent Error Detection for FFT Networks
IEEE Transactions on Computers
Concurrent Error Detection in Fast Unitary Transform Algorithms
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
Concurrent Error Detection in Wavelet Lifting Transforms
IEEE Transactions on Computers
On concurrent error location and correction of FFT networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The algorithm-based fault tolerance techniques have been proposed to obtain reliableresults at very low hardware overhead. Even though 100% fault coverage can betheoretically obtained by using these techniques, the system performance, i.e., faultcoverage and throughput, can be drastically reduced due to many practical problems,e.g., round-off errors. A novel algorithm-based fault tolerance scheme is proposed forfast Fourier transform (FFT) networks. It is shown that the proposed scheme achieves100% fault coverage theoretically. An accurate measure of the fault coverage for FFTnetworks is provided by taking the round-off error into account. The proposed scheme isshown to provide concurrent error detection capability to FFT networks with lowhardware overhead, high throughput, and high fault coverage.