Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
IEEE Transactions on Computers
A Fault-Tolerant FFT Processor
IEEE Transactions on Computers
Discrete-time signal processing
Discrete-time signal processing
Easily Testable Iterative Logic Arrays
IEEE Transactions on Computers
Testing and diagnosis of FFT arrays
Journal of VLSI Signal Processing Systems - Special issue: algorithms and parallel VSLI architecture
On the testability of array structures for FFT computation
Journal of Electronic Testing: Theory and Applications
C-testable design techniques for iterative logic arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
COBRA: a 100-MOPS single-chip programmable and expandable FFT
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Algorithm-Based Fault Tolerance for FFT Networks
IEEE Transactions on Computers
An Efficient Algorithm-Based Concurrent Error Detection for FFT Networks
IEEE Transactions on Computers
A Novel Concurrent Error Detection Scheme for FFT Networks
IEEE Transactions on Parallel and Distributed Systems
Designing Self-Testable Cellular Arrays
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
A concurrent fault-detection scheme for FFT processors
ATS '97 Proceedings of the 6th Asian Test Symposium
Diagnosis and Design for Diagnosability for Internet Routers
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
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We consider offline testing, design-for-testability, and diagnosis for fast Fourier transform (FFT) networks. A practical FFT chip can contain millions of gates, so effective testing and fault-tolerance techniques usualiy are required in order to guarantee high-quality products. We propose M-testability conditions for FFT butterfly, omega, and flip networks at the double-multiply-subtract-add (DMSA) module level. A novel design-for-testability technique based on the functional bijectivity property of the specified modules to detect faults other than the cell faults is presented. It guarantees 100% Combinational fault coverage with negligible hardware overhead--about 0.17% for an FFT network with 16-bit operand words, independent of the network size. Our design requires fewer test vectors compared with previous ones--a factor of up to 1/(6 × 25n), where n is the word length. We also propose C-diagnosability conditions and a C-diagnosable FFT network design. By properly exchanging and blocking certain fault propagation paths, a faulty DMSA module can be located using a two-phase deterministic algorithm. The blocking mechanism can be implemented with no additional hardware. Compared with previous schemes, our design reduces the diagnosis complexity from O(N) to O(1). For both testing and diagnosis, the hardware overhead for our approach is only about 0.43% for 16-bit numbers regardless of the FFT network size.