Efficient FFT network testing and diagnosis schemes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast: FFT ASIC automated synthesis
Integration, the VLSI Journal
A small-area high-performance 512-point 2-dimensional FFT single-chip processor
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Distributed Arithmetic based Split-Radix FFT
Journal of Signal Processing Systems
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This paper presents an optimized column fast Fourier transform (FFT) architecture, which utilizes bit-serial arithmetic and dynamic reconfiguration to achieve a complete overlap between computation and communication. As a result, for a clock rate of 40 MHz, the system can compute a 24-b precision 1K point complex FFT transform in 9.2 /spl mu/s, far surpassing the performance of any existing FFT systems.