A small-area high-performance 512-point 2-dimensional FFT single-chip processor

Authors:
Naoto Miyamoto;Leo Karnan;Kazuyuki Maruo;Koji Kotani;Tadahiro Ohmi
Affiliations:
University of Tohoku, Aramaki, Aoba, Sendai, Japan;University of Tohoku, Aramaki, Aoba, Sendai, Japan;Advantest Laboratories Ltd., Matsubara, Kamiayashi, Aoba, Sendai, Japan;University of Tohoku, Aramaki, Aoba, Sendai, Japan;University of Tohoku, Aramaki, Aoba, Sendai, Japan
Venue:
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Year:
2004

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Abstract

We have designed an FFT processor based on the 2-stage cached-memory architecture, which integrates 552,000 transistors within an area of 2.8 x 2.8 mm2 with CMOS 0.35μm triple-layer-metal process. This processor can execute a 512-point, 36-bit-complex fixed-point data format, 1-dimensional FFT in 23.2 μsec and a 2-dimensional one is only 23.8 msec at 133MHz operation. We have measured this processor consumes 439.6mW at 3.3V, 100MHz operation.