COBRA: a 100-MOPS single-chip programmable and expandable FFT
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
OFDM for Wireless Multimedia Communications
OFDM for Wireless Multimedia Communications
Self Sorting Radix_2 FFT on FPGA using Parallel Pipelined Distributed Arithmetic Blocks
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
New Hardware Realizations of Nonrecursive Digital Filters
IEEE Transactions on Computers
The Counting Recursive Digital Filter
IEEE Transactions on Computers
A Pipelined Distributed Arithmetic PFFT Processor
IEEE Transactions on Computers
High-speed and low-power split-radix FFT
IEEE Transactions on Signal Processing
A Low Power and Small Area FFT Processor for OFDM Demodulator
IEEE Transactions on Consumer Electronics
An Area-Efficient FFT Architecture for OFDM Digital Video Broadcasting
IEEE Transactions on Consumer Electronics
Low-cost reconfigurable VLSI architecture for fast fourier transform
IEEE Transactions on Consumer Electronics
IEEE Communications Magazine
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In this paper we have designed a Split-radix type FFT unit without using multipliers. All the complex multiplications required for this type of FFT are implemented using Distributed Arithmetic (DA) technique. A method is incorporated to overcome the result overflow problem introduced by DA method. Proposed FFT architecture is implemented in 180 nm CMOS technology at a supply voltage of 1.8 V.