IEEE Transactions on Computers
New Hardware Realizations of Nonrecursive Digital Filters
IEEE Transactions on Computers
A Note on Base -2 Arithmetic Logic
IEEE Transactions on Computers
On Little's Digital Filtering Algorithm
IEEE Transactions on Computers
Rounding and Truncation in Radix (-2) Systems
IEEE Transactions on Computers
Fast Hardware Fourier Transformation Through Counting
IEEE Transactions on Computers
IEEE Transactions on Computers
An Algorithm for High-Speed Digital Filters
IEEE Transactions on Computers
A Realization of the RAM Digital Filter
IEEE Transactions on Computers
Arithmetic Algorithms in a Negative Base
IEEE Transactions on Computers
On Multiple Operand Addition of Signed Binary Numbers
IEEE Transactions on Computers
Layout aware optimization of high speed fixed coefficient FIR filters for FPGAs
International Journal of Reconfigurable Computing
Distributed Arithmetic based Split-Radix FFT
Journal of Signal Processing Systems
Hi-index | 15.01 |
Analysis of the bit-level operations involved in the convolutions realizing recursive digital filters leads to hardware designs of such filters based on the operation of counting. Various designs realizing both the canonic and "direct" forms are presented with particular emphasis on low-cost low-speed high-flexibility machines.