On Multiple Operand Addition of Signed Binary Numbers

Authors:
D. P. Agrawal;T. R. N. Rao
Affiliations:
Department of Electrical and Computer Engineering, Wayne State University;-
Venue:
IEEE Transactions on Computers
Year:
1978

Citing 9
Cited 3

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The Quasi-Serial Multiplier

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New Hardware Realizations of Nonrecursive Digital Filters

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The Counting Recursive Digital Filter

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Fast Hardware Fourier Transformation Through Counting

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Arithmetic Algorithms in a Negative Base

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Parallel Counters

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Multiple Addition by Residue Threshold Functions and Their Representation by Array Logic

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A Simple High-Speed Multiplier Design

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On Negabinary-Binary Arithmetic Relationships and Their Hardware Reciprocity

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Bit-Sequential Arithmetic for Parallel Processors

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Abstract

Recent application of negabinary number systems in signal processing has evoked the question of the suitability of binary base. Many proposals for multioperand addition of unsigned binary numbers are available in the literature. Here, the addition of two numbers in 2's complement notation-has been extended to n signed summands. The time delay remains the same as that of processing n unsigned numbers. This method shows new promises for its application to signal processing.