Adder With Distributed Control
IEEE Transactions on Computers
AFIPS '69 (Fall) Proceedings of the November 18-20, 1969, fall joint computer conference
Universal logic modules implemented using LSI memory techniques
AFIPS '71 (Fall) Proceedings of the November 16-18, 1971, fall joint computer conference
An On-Line Square Root Algorithm
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
A Synthesizing Method for Large Parallel Counters with a Network of Smaller Ones
IEEE Transactions on Computers
A Compact High-Speed Parallel Multiplication Scheme
IEEE Transactions on Computers
On Multiple Operand Addition of Signed Binary Numbers
IEEE Transactions on Computers
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In multioperand additions p summands can be compressed into q summands by adding along the columns independently. For a given column Z with Boolean elements {zi}, this sum is 驴rk2k, where rk equals a residue threshold function R(2k, 2k+1 |Z), defined by the proposition R(t, m |Z) 驴 t 驴 (驴zi) mod m. The hardware realization is particularly simple using symmetry-adapted READ-ONLY storage (ROS) array logic.