Bounds to Complexities of Networks for Sorting and for Switching
Journal of the ACM (JACM)
IEEE Transactions on Computers
Multiple Operand Addition and Multiplication
IEEE Transactions on Computers
Arithmetic Networks and Their Minimization Using a New Line of Elementary Units
IEEE Transactions on Computers
A Synthesizing Method for Large Parallel Counters with a Network of Smaller Ones
IEEE Transactions on Computers
IEEE Transactions on Computers
Counting Responders in an Associative Memory
IEEE Transactions on Computers
Multiple Addition by Residue Threshold Functions and Their Representation by Array Logic
IEEE Transactions on Computers
Synthesis of Generalized Parallel Counters
IEEE Transactions on Computers
| Hi-index | 14.98 |
A subclass of generalized parallel counters, called parallel compressors, is introduced in this correspondence. Under present-day packaging technology, parallel compressors with their higher compression ratio and fewer input/output pins are more efficient in multiple operand addition and multiplication than parallel counters. Cost and time bounds are obtained for schemes using parallel compressors for reduction of N summands to m summands. Furthermore, a method for synthesizing large parallel counters using only one type of parallel compressor is given.