Low-complexity FFT/IFFT IP hardware macrocells for OFDM and MIMO-OFDM CMOS transceivers
Microprocessors & Microsystems
Reconfigurable VLSI architecture for FFT processor
MUSP'09 Proceedings of the 9th WSEAS international conference on Multimedia systems & signal processing
Reconfigurable VLSI architecture for FFT processor
WSEAS Transactions on Circuits and Systems
A low area pipelined FFT processor for OFDM based systems
WiCOM'09 Proceedings of the 5th International Conference on Wireless communications, networking and mobile computing
Low-power and high-speed CORDIC-based split-radix FFT processor for OFDM systems
Digital Signal Processing
Low-Power Application-Specific Processor for FFT Computations
Journal of Signal Processing Systems
Distributed Arithmetic based Split-Radix FFT
Journal of Signal Processing Systems
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The FFT (fast Fourier transform) processor is the most speed and power consumption critical part in the orthogonal frequency division multiplexing (OFDM) communication system. In this paper, a low power consumption and small area FFT processor architecture suitable for OFDM demodulators is proposed. In order to meet the requirements of high-speed data throughput and low power and small area consumption, distributed memory architecture is developed to meet the requirement of non-stopping and high-speed data throughput. One clock-cycle mixed radix-2/4 butterfly architecture is proposed for OFDM. Meanwhile, due to the two radix-2 and radix-4 butterflies share in the two complex multipliers, the FFT processor with the proposed radix-2/4 butterfly can make the 64% power consumption reduction and the 35% gate count reduction, respectively. Performance analysis shows that the proposed FFT architecture can meet the requirement of OFDM demodulators in DVB-T and other high speed wireless applications.