PARELEC '06 Proceedings of the international symposium on Parallel Computing in Electrical Engineering
Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations
IEEE Transactions on Computers
IEEE Transactions on Computers
Fixed-Point Error Analysis of CORDIC Arithmetic for Special-Purpose Signal Processors
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
High-speed and low-power split-radix FFT
IEEE Transactions on Signal Processing
On the Fixed-Point Accuracy Analysis of FFT Algorithms
IEEE Transactions on Signal Processing - Part I
An approach to simplify the design of IFFT/FFT cores for OFDM systems
IEEE Transactions on Consumer Electronics
A Low Power and Small Area FFT Processor for OFDM Demodulator
IEEE Transactions on Consumer Electronics
Low-Power Hypercube Divided Memory FFT Engine Using 3D Integration
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Function approximation on decimal operands
Digital Signal Processing
Hi-index | 0.00 |
This paper presents a CORDIC (Coordinate Rotation Digital Computer)-based split-radix fast Fourier transform (FFT) core for OFDM systems, for example, Ultra Wide Band (UWB), Asymmetric Digital Subscriber Line (ADSL), Digital Audio Broadcasting (DAB), Digital Video Broadcasting - Terrestrial (DVB-T), Very High Bitrate DSL (VHDSL), and Worldwide Interoperability for Microwave Access (WiMAX). The high-speed 128/256/512/1024/2048/4096/8192-point FFT processor has been implemented by 0.18 @mm (1p6m) at 1.8 V, in which all the control signals are generated internally. This programmable FFT processor outperforms the conventional ones in terms of both power consumption and core area.