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Journal of the ACM (JACM)
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Introduction to VLSI Systems
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
LAYOUT FOR THE SHUFFLE-EXCHANGE GRAPH AND LOWER BOUND TECHNIQUES FOR VLSI
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A complexity theory for VLSI
Parallel Processing with the Perfect Shuffle
IEEE Transactions on Computers
Very Fast Fourier Transform Algorithms Hardware for Implementation
IEEE Transactions on Computers
Generalized Connection Networks for Parallel Processor Intercommunication
IEEE Transactions on Computers
The cube-connected-cycles: A versatile network for parallel computation
SFCS '79 Proceedings of the 20th Annual Symposium on Foundations of Computer Science
A combinatorial limit to the computing power of V.L.S.I. circuits
SFCS '80 Proceedings of the 21st Annual Symposium on Foundations of Computer Science
On driving many long lines in a VLSI layout
SFCS '82 Proceedings of the 23rd Annual Symposium on Foundations of Computer Science
Design of 2.5-micrometer Josephson current injection logic (CIL)
IBM Journal of Research and Development
VLSI Architectures for multidimensional fourier transform processing
IEEE Transactions on Computers
A New Approach to Pipeline FFT Processor
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
A Fully Pipelined Systolic Array for Sinusoidal Sequence Generation
IEEE Transactions on Computers
The VLSI Complexity of Sorting
IEEE Transactions on Computers
Reconfigurable VLSI architecture for FFT processor
MUSP'09 Proceedings of the 9th WSEAS international conference on Multimedia systems & signal processing
Reconfigurable VLSI architecture for FFT processor
WSEAS Transactions on Circuits and Systems
Integration, the VLSI Journal
Fully Systolic FFT Architecture for Giga-sample Applications
Journal of Signal Processing Systems
Low-power and high-speed CORDIC-based split-radix FFT processor for OFDM systems
Digital Signal Processing
A new FFT architecture for 4 × 4 MIMO-OFDMA systems with variable symbol lengths
IIT'09 Proceedings of the 6th international conference on Innovations in information technology
A systolic VLSI architecture for multi-dimensional transforms
ICASSP'93 Proceedings of the 1993 IEEE international conference on Acoustics, speech, and signal processing: plenary, special, audio, underwater acoustics, VLSI, neural networks - Volume I
ICASSP'93 Proceedings of the 1993 IEEE international conference on Acoustics, speech, and signal processing: digital speech processing - Volume III
On concurrent error location and correction of FFT networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
New area-time lower bounds for the multidimensional DFT
CATS 2011 Proceedings of the Seventeenth Computing on The Australasian Theory Symposium - Volume 119
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This paper surveys nine designs for VLSI circuits that compute N-element Fourier transforms. The largest of the designs requires O(N2 log N) units of silicon area; it can start a new Fourier transform every O(log N) time units. The smallest designs have about 1/Nth of this throughput, but they require only 1/Nth as much area.