A New Approach to Pipeline FFT Processor
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
Novel design of multiplier-less FFT processors
Signal Processing
Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations
IEEE Transactions on Computers
Complex Number Arithmetic with Odd- Valued Logic
IEEE Transactions on Computers
IEEE Transactions on Computers
The VLSI Complexity of Sorting
IEEE Transactions on Computers
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
A new FFT concept for efficient VLSI implementation: part 1 - butterfly processing element
DSP'09 Proceedings of the 16th international conference on Digital Signal Processing
An architecture for a VLSI FFT processor
Integration, the VLSI Journal
A generalized mixed-radix algorithm for memory-based FFT processors
IEEE Transactions on Circuits and Systems II: Express Briefs
A high throughput FFT processor with no multipliers
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
A CORDIC processor for FFT computation and its implementation using gallium arsenide technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 14.99 |
A new method of deriving very fast Fourier transform (FFT) algorithms is described. The resulting algorithms do not employ multiplication and have a form suitable for high performance hardware implementations. The complexity of the algorithms compares favorably to the recent results of Winograd [1].