A chip set for pipeline and parallel pipeline FFT architectures
Journal of VLSI Signal Processing Systems - Special issue on the Canadian conference on VLSI
Very Fast Fourier Transform Algorithms Hardware for Implementation
IEEE Transactions on Computers
Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations
IEEE Transactions on Computers
A new FFT concept for efficient VLSI implementation: part ii - parallel pipelined processing
DSP'09 Proceedings of the 16th international conference on Digital Signal Processing
A Modified Split-Radix FFT With Fewer Arithmetic Operations
IEEE Transactions on Signal Processing
Novel Memory Reference Reduction Methods for FFT Implementations on DSP Processors
IEEE Transactions on Signal Processing
A new FFT concept for efficient VLSI implementation: part ii - parallel pipelined processing
DSP'09 Proceedings of the 16th international conference on Digital Signal Processing
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This article describes a new approach for higher radix butterflies suitable for pipeline implementation. Based on the butterfly computation introduced by Cooley-Tukey [1], we introduce a novel approach for the factorization of the Discrete Fourier Transform (DFT), by redefining the butterfly computation, which is more suitable for efficient VLSI implementation. This proposed factorization motivated us to present a new concept of a radix-r Fast Fourier Transform (FFT), in which the radix-r butterfly computation concept was form ulated as composite engines to implement each of the butterfly computations. This concept enables the radix r butterfly-processing element (BPE) to be designed by maintaining only one complex value multiplier in the butterfly critical path for any given r. Algorithmic description and performance of low complexity FFT method are considered in this paper and parallel pipelined FFT in a companion paper [15], Part II Parallel Pipelined FFT Processing.