Number Theory in Digital Signal Processing
Number Theory in Digital Signal Processing
Notes on Shuffle/Exchange-Type Switching Networks
IEEE Transactions on Computers
Very Fast Fourier Transform Algorithms Hardware for Implementation
IEEE Transactions on Computers
Fourier Transform Computers Using CORDIC Iterations
IEEE Transactions on Computers
High-speed convolution and correlation
AFIPS '66 (Spring) Proceedings of the April 26-28, 1966, Spring joint computer conference
Fast Fourier Transforms: for fun and profit
AFIPS '66 (Fall) Proceedings of the November 7-10, 1966, fall joint computer conference
A unified algorithm for elementary functions
AFIPS '71 (Spring) Proceedings of the May 18-20, 1971, spring joint computer conference
A New Approach to Pipeline FFT Processor
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
Novel design of multiplier-less FFT processors
Signal Processing
Hybrid Wordlength Optimization Methods of Pipelined FFT Processors
IEEE Transactions on Computers
Pruning fast Fourier transform algorithm design using group-based method
Signal Processing
Long-Point FFT Processing Based on Twiddle Factor Table Reduction
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Reconfigurable VLSI architecture for FFT processor
MUSP'09 Proceedings of the 9th WSEAS international conference on Multimedia systems & signal processing
Reconfigurable VLSI architecture for FFT processor
WSEAS Transactions on Circuits and Systems
Pipeline FFT architectures optimized for FPGAs
International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
Radix rkFFTs: matricial representation and SDC/SDF pipeline implementation
IEEE Transactions on Signal Processing
A new FFT concept for efficient VLSI implementation: part 1 - butterfly processing element
DSP'09 Proceedings of the 16th international conference on Digital Signal Processing
Fully Systolic FFT Architecture for Giga-sample Applications
Journal of Signal Processing Systems
Low-power and high-speed CORDIC-based split-radix FFT processor for OFDM systems
Digital Signal Processing
Low-Power Hypercube Divided Memory FFT Engine Using 3D Integration
ACM Transactions on Design Automation of Electronic Systems (TODAES)
FPGA implementation and testing of a 128 FFT for a MB-OFDM receiver
Analog Integrated Circuits and Signal Processing
FPGA implementation of a novel architecture for performance enhancement of Radix-2 FFT
ACM SIGARCH Computer Architecture News
Pipelined parallel FFT architectures via folding transformation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Pipelined radix-2k feedforward FFT architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In some signal processing applications, it is desirable to build very high performance fast Fourier transform (FFT) processors. To meet the performance requirements, these processors are typically highly pipelined. Until the advent of VLSI, it was not possible to build a single chip which could be used to construct pipeline FFT processors of a reasonable size. However, VLSI implementations have constraints which differ from those of discrete implementations, requiring another look at some of the typical FFT'algorithms in the light of these constraints.