A radix-8 wafer scale FFT processor
Journal of VLSI Signal Processing Systems - Special issue: 1990 Workshop on VLSI signal processing
Discrete-time signal processing (2nd ed.)
Discrete-time signal processing (2nd ed.)
ILP-based cost-optimal DSP synthesis with module selection and data format conversion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Handbook of Real-Time Fast Fourier Transforms: Algorithms to Product Testing
Handbook of Real-Time Fast Fourier Transforms: Algorithms to Product Testing
Fast Prototyping of Datapath-Intensive Architectures
IEEE Design & Test
A New Approach to Pipeline FFT Processor
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations
IEEE Transactions on Computers
Fourier Transform Computers Using CORDIC Iterations
IEEE Transactions on Computers
Radix-2 decimation-in-frequency algorithm for the computation ofthe real-valued FFT
IEEE Transactions on Signal Processing
TDCS, OFDM, and MC-CDMA: a brief tutorial
IEEE Communications Magazine
High-level DSP synthesis using concurrent transformations, scheduling, and allocation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Microprocessors & Microsystems
Hi-index | 0.00 |
This paper presents a novel approach to develop parallel pipelined architectures for the fast Fourier transform (FFT). A formal procedure for designing FFT architectures using folding transformation and register minimization techniques is proposed. Novel parallel-pipelined architectures for the computation of complex and real valued fast Fourier transform are derived. For complex valued Fourier transform (CFFT), the proposed architecture takes advantage of under utilized hardware in the serial architecture to derive L-parallel architectures without increasing the hardware complexity by a factor of L. The operating frequency of the proposed architecture can be decreased which in turn reduces the power consumption. Further, this paper presents new parallel-pipelined architectures for the computation of real-valued fast Fourier transform (RFFT). The proposed architectures exploit redundancy in the computation of FFT samples to reduce the hardware complexity. A comparison is drawn between the proposed designs and the previous architectures. The power consumption can be reduced up to 37% and 50% in 2-parallel CFFT and RFFT architectures, respectively. The output samples are obtained in a scrambled order in the proposed architectures. Circuits to reorder these scrambled output sequences to a desired order are presented.