A new parallel architecture for sparse matrix computation based on finite projective geometries
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Proceedings of the 37th Annual Design Automation Conference
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Floorplan-aware automated synthesis of bus-based communication architectures
Proceedings of the 42nd annual Design Automation Conference
IEEE Transactions on Parallel and Distributed Systems
Performance, Algorithmic, and Robustness Attributes of Perfect Difference Networks
IEEE Transactions on Parallel and Distributed Systems
Creating Explicit Communication in SoC Models Using Interactive Re-Coding
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
IEEE Transactions on Signal Processing
Efficient folded VLSI architectures for linear prediction error filters
Proceedings of the great lakes symposium on VLSI
Low-density parity-check codes based on finite geometries: a rediscovery and new results
IEEE Transactions on Information Theory
Mapping interleaving laws to parallel turbo and LDPC decoder architectures
IEEE Transactions on Information Theory
Automatic Layer-Based Generation of System-On-Chip Bus Communication Models
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interval graph algorithms for two-dimensional multiple folding of array-based VLSI layouts
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pipelined parallel FFT architectures via folding transformation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Semi-parallel, or folded, VLSI architectures are used whenever hardware resources need to be saved. Most recent applications that are based on Projective Geometry (PG) based balanced bipartite graphs also fall in this category. Many of these applications are actively being researched upon, especially in the area of coding theory and matrix computations. Almost all these applications need bipartite graphs of the order of tens of thousands in practice, whose nodes represent parallel processing. To reduce its implementation cost, reducing amount of hardware resources is an important engineering objective. In this paper, we provide a high-level, top-down design methodology to design optimal semi-parallel architectures for applications, whose Data Flow Graph (DFG) is based on PG bipartite graph. Unlike many other folding schemes, the topology of connections between physical elements nodesdoes not change at runtime in this methodology. Hence the folding scheme achieves the best possible throughput, in lack of any overhead of shuffling data across memories while scheduling another computation on the same processing unit. Another advantage is the ease of implementation. To lessen the throughput loss due to folding, we also incorporate a multi-tier pipelining strategy in the design methodology. A C++-based synthesis tool has been developed and tested for automatic generation of RTL models, and is publicly available. A specific high-performance design of a low-density parity check (LDPC) decoder based on this methodology was worked out in past, and has been patent pending.