Protocol selection and interface generation for HW-SW codesign
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Bus-based communication synthesis on system level
ACM Transactions on Design Automation of Electronic Systems (TODAES)
MOCSYN: multiobjective core-based single-chip system synthesis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 38th annual Design Automation Conference
Constraint-driven communication synthesis
Proceedings of the 39th annual Design Automation Conference
Latency-guided on-chip bus network design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Efficient exploration of the SoC communication architecture design space
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
AMBA: Enabling Reusable On-Chip Designs
IEEE Micro
System-Level Point-to-Point Communication Synthesis Using Floorplanning Information
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
SEAS: a system for early analysis of SoCs
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Extending the transaction level modeling approach for fast communication architecture exploration
Proceedings of the 41st annual Design Automation Conference
Automated Bus Generation for Multiprocessor SoC Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Fast Exploration of Bus-Based On-Chip Communication Architectures
CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On wirelength estimations for row-based placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect performance estimation models for design planning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Constraint-driven bus matrix synthesis for MPSoC
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Application specific NoC design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint
Proceedings of the 43rd annual Design Automation Conference
Floorplan driven leakage power aware IP-based SoC design space exploration
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
System-level power-performance trade-offs in bus matrix communication architecture synthesis
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Early wire characterization for predictable network-on-chip global interconnects
Proceedings of the 2007 international workshop on System level interconnect prediction
Designing application-specific networks on chips with floorplan information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Synthesis of predictable networks-on-chip-based interconnect architectures for chip multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
NoC topology synthesis for supporting shutdown of voltage islands in SoCs
Proceedings of the 46th Annual Design Automation Conference
Topology/floorplan/pipeline co-design of cascaded crossbar bus
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Physical synthesis of bus matrix for high bandwidth low power on-chip communications
Proceedings of the 19th international symposium on Physical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SunFloor 3D: a tool for networks on chip topology synthesis for 3D systems on chips
Proceedings of the Conference on Design, Automation and Test in Europe
Sunfloor 3D: a tool for networks on chip topology synthesis for 3-D systems on chips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Topology synthesis for low power cascaded crossbar switches
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A multi-level design methodology of multistage interconnection network for MPSOCs
International Journal of Computer Applications in Technology
Microprocessors & Microsystems
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As System-on-Chip (SoC) designs become more complex, it is becoming harder to design communication architectures to handle the ever increasing volumes of inter-component communication. Manual traversal of the vast communication design space to synthesize a communication architecture that meets performance requirements becomes infeasible. In this paper, we address this problem by proposing an automated approach for synthesizing cost-effective, bus-based communication architectures that satisfy the performance constraints in a design. Our synthesis flow also incorporates a high-level floorplanning and wire delay estimation engine to evaluate the feasibility of the synthesized bus architecture and detect timing violations early in the design flow. We present case studies of network communication SoC subsystems for which we synthesized bus architectures, detected timing violations and generated core placements in a matter of hours instead of several days it took for a manual effort.