Technology and design challenges for low power and high performance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
An Introduction to VLSI Physical Design
An Introduction to VLSI Physical Design
Latency-guided on-chip bus network design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
SEAS: a system for early analysis of SoCs
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 1
System level leakage reduction considering the interdependence of temperature and leakage
Proceedings of the 41st annual Design Automation Conference
Temperature-aware global placement
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Thermal-Aware Floorplanning Using Genetic Algorithms
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Floorplan-aware automated synthesis of bus-based communication architectures
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
Hotspots elimination and temperature flattening in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Multi-million gate System-on-Chip (SoC) designs increasingly rely on Intellectual Property (IP) blocks. However, due to technology scaling the leakage power consumption of the IP blocks has risen thus leading to possible thermal runaway. In IP-based design there has been a disconnect between system level design and physical level steps such as floorplanning which can lead to failures in manufactured chips. This necessitates coupling between system level and physical level design steps. The leakage power of an IP-block increases with its temperature which is dependent on the SoC's floorplan due to thermal diffusion. We have observed that different floorplans of the same SoC can have up to 3X difference in leakage power. Hence the system designer needs to be aware of this design space between floorplans and leakage power. We propose a leakage aware exploration (LAX) framework which enables the system designer to create this design space early in the design cycle and provides an opportunity to make changes in the system design. We show the size of the design space generated by applying LAX on ten industrial SoC designs from Freescale Semiconductor Inc. and observe that the leakage power can vary by as much as 190% for 65% difference in the inactive area.