Latency-guided on-chip bus network design

Authors:
Milenko Drinic;Darko Kirovski;Seapahn Meguerdichian;Miodrag Potkonjak
Affiliations:
University of California, Los Angeles, CA;University of California, Los Angeles, CA;University of California, Los Angeles, CA;University of California, Los Angeles, CA
Venue:
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Year:
2000

Citing 11
Cited 20

Optimal wiresizing for interconnects with multiple sources

ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Necessary and Sufficient Condition for Deadlock-Free Routing in Cut-Through and Store-and-Forward Networks

IEEE Transactions on Parallel and Distributed Systems
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems

MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Improved delay prediction for on-chip buses

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Engineering change: methodology and applications to behavioral and system synthesis

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A methodology for correct-by-construction latency insensitive design

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Rethinking Deep-Submicron Circuit Design

Computer
Computers and Intractability: A Guide to the Theory of NP-Completeness

Computers and Intractability: A Guide to the Theory of NP-Completeness
Formal implementation verification of the bus interface unit for the Alpha 21264 microprocessor

ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
An analytical delay model for RLC interconnects

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Buffer insertion for noise and delay optimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Scalable and flexible cosimulation of SoC designs with heterogeneous multi-processor target architectures

Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A generic wrapper architecture for multi-processor SoC cosimulation and design

Proceedings of the ninth international symposium on Hardware/software codesign
Throughput-driven IC communication fabric synthesis

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
System-Level Point-to-Point Communication Synthesis Using Floorplanning Information

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Guaranteeing the quality of services in networks on chip

Networks on chip
Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip

Proceedings of the conference on Design, automation and test in Europe - Volume 1
SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A high performance bus communication architecture through bus splitting

Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Floorplan-aware automated synthesis of bus-based communication architectures

Proceedings of the 42nd annual Design Automation Conference
Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Schedule-aware performance estimation of communication architecture for efficient design space exploration

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automated throughput-driven synthesis of bus-based communication architectures

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
FABSYN: floorplan-aware bus architecture synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Floorplan driven leakage power aware IP-based SoC design space exploration

CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
On-Chip Communication Architectures: System on Chip Interconnect

On-Chip Communication Architectures: System on Chip Interconnect
SAMBA-bus: A high performance bus architecture for system-on-chips

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Topology/floorplan/pipeline co-design of cascaded crossbar bus

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CAPPS: a framework for power-performance tradeoffs in bus-matrix-based on-chip communication architecture synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The Lotterybus on-chip communication architecture

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient exploration of bus-based system-on-chip architectures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Deep submicron technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in critical paths being dominated by global interconnect rather than gate delays. Second, ultra high level of integration mandates design of systems-on-chip that encompass numerous intra-synchronous blocks with decreased functional granularity and increased communication demands. To address these issues we have developed an on-chip bus network design methodology and corresponding set of tools which, for the first time, close the synthesis loop between system and physical design. The approach has three components: a communication profiler, a bus network designer, and a fast approximate floorplanner. The communication profiler collects run-time information about the traffic between system cores. The bus network design component optimizes the bus network structure by coordinating information from the other two components. The floorplanner aims at creating a feasible floorplan and to communicate information about the most constrained parts of the network.