A two moment RC delay metric for performance optimization
ISPD '00 Proceedings of the 2000 international symposium on Physical design
RLC interconnect delay estimation via moments of amplitude and phase response
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Validation and test generation for oscillatory noise in VLSI interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Reducing bus delay in submicron technology using coding
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Min/max on-chip inductance models and delay metrics
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 38th annual Design Automation Conference
Fast and accurate wire delay estimation for physical synthesis of large ASICs
Proceedings of the 12th ACM Great Lakes symposium on VLSI
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
PERI: a technique for extending delay and slew metrics to ramp inputs
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Reduced Order Modeling for RLC Interconnect Tree Using Hurwitz Polynomial
Analog Integrated Circuits and Signal Processing
Effects of global interconnect optimizations on performance estimation of deep submicron design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Hurwitz stable reduced order modeling for RLC interconnect trees
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
An "effective" capacitance based delay metric for RC interconnect
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Latency-guided on-chip bus network design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Closed form expressions for extending step delay and slew metrics to ramp inputs
Proceedings of the 2003 international symposium on Physical design
A practical approach to model long MIS interconnects in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A delay metric for RC circuits based on the Weibull distribution
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Delay and slew metrics using the lognormal distribution
Proceedings of the 40th annual Design Automation Conference
Improved a priori terconnect predictions and technology extrapolation in the GTX system
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Maximizing throughput over parallel wire structures in the deep submicrometer regime
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Simplified delay design guidelines for on-chip global interconnects
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Analytic Modeling of Interconnects for Deep Sub-Micron Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Low-power on-chip communication based on transition-aware global signaling (TAGS)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Robust analytical gate delay modeling for low voltage circuits
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A Mixed Boundary Element Method for Extracting Frequency- Inductances of 3D Interconnects
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
Digital Circuit Optimization via Geometric Programming
Operations Research
Effects of coupling capacitance and inductance on delay uncertainty and clock skew
Proceedings of the 44th annual Design Automation Conference
A delay model for interconnect trees based on ABCD matrix
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
VLSI: an investigation into the effect of non-uniform distribution of current on crosstalk noise
EHAC'08 Proceedings of the 7th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Analytical timing model for inductance-dominant interconnect based on traveling wave propagation
Microelectronics Journal
Evaluating the effects of temperature gradients and currents nonuniformity in on-chip interconnects
Microelectronics Journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High speed interconnect data dependent jitter analysis
Microelectronics Journal
Interconnect delay and slew metrics using the beta distribution
Proceedings of the Conference on Design, Automation and Test in Europe
Decoupling capacitor planning with analytical delay model on RLC power grid
Proceedings of the Conference on Design, Automation and Test in Europe
Crosstalk modeling for coupled RLC interconnects with application to shield insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the impact of on-chip inductance on signal nets under the influence of power grid noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power characteristics of inductive interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient delay and crosstalk modeling of RLC interconnects using delay algebraic equations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast waveform estimation (FWE) for timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient delay metric on RC interconnects under saturated ramp inputs
ICCSA'06 Proceedings of the 2006 international conference on Computational Science and Its Applications - Volume Part IV
An improved Elmore delay model for VLSI interconnects
Mathematical and Computer Modelling: An International Journal
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields
A novel theory on parallel repeater-insertion methodologies for long on-chip interconnects
International Journal of Circuit Theory and Applications
High-performance gate sizing with a signoff timer
Proceedings of the International Conference on Computer-Aided Design
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Elmore delay has been widely used to estimate interconnect delays in the performance-driven synthesis and layout of very-large-scale-integration (VLSI) routing topologies. For typical RLC interconnections, however, Elmore delay can deviate significantly from SPICE-computed delay, since it is independent of inductance of the interconnect and rise time of the input signal. Here, we develop an analytical delay model based on first and second moments to incorporate inductance effects into the delay estimate for interconnection lines under step input. Delay estimates using our analytical model are within 15% of SPICE-computed delay across a wide range of interconnect parameter values. We also extend our delay model for estimation of source-sink delays in arbitrary interconnect trees. We observe significant improvement in the accuracy of delay estimates for interconnect trees when compared to the Elmore model, yet our estimates are as easy to compute as Elmore delay. Evaluation of our analytical models is several orders of magnitude faster than simulation using SPICE. We also illustrate the application of our model in controlling response undershoot/overshoot and reducing interconnect delay through constraints on the moments