Modeling and characterization of long on-chip interconnections for high-performance microprocessors
IBM Journal of Research and Development
An efficient analytical model of coupled on-chip RLC interconnects
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
An analytical delay model for RLC interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Equivalent Elmore delay for RLC trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Novel signal integrity verification models for inductance-dominant RLC interconnect lines are developed by using a traveling-wave-based waveform approximation (TWA) technique. The multi-coupled line responses are decoupled into the eigenmodes of the system in order to exploit the TWA technique. Then, the response signals are mathematically represented by the linear combination of each eigenmode response based on TWA, followed by reporting the signal integrity models for the multi-coupled lines. The signal integrity of VLSI circuit interconnects has a strong correlation with input signal switching-patterns in the multiple lines. With the proposed analytic signal integrity models, the switching-dependent signal delay, crosstalk, ringing, and glitches of the inductance-dominant RLC interconnect lines can be accurately as well as efficiently determined. It is shown that the models have excellent agreement with SPICE simulations.