Reduced-order modeling of large linear subcircuits via a block Lanczos algorithm
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Modeling and characterization of long on-chip interconnections for high-performance microprocessors
IBM Journal of Research and Development
Reduced-order modeling of large passive linear circuits by means of the SYPVL algorithm
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
An efficient analytical model of coupled on-chip RLC interconnects
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Digital Signal Integrity: Modeling and Simulation with Interconnects and Packages
Digital Signal Integrity: Modeling and Simulation with Interconnects and Packages
Analysis of Multiconductor Transmission Lines
Analysis of Multiconductor Transmission Lines
Numerical Methods for Engineers: With Programming and Software Applications
Numerical Methods for Engineers: With Programming and Software Applications
An analytical delay model for RLC interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Equivalent Elmore delay for RLC trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Equivalent circuit model of on-wafer CMOS interconnects for RFICs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient delay and crosstalk modeling of RLC interconnects using delay algebraic equations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-aggressor capacitive and inductive coupling noise modeling and mitigation
Microelectronics Journal
Hi-index | 0.00 |
Novel signal integrity verification models and algorithms for inductance-effect- prominent RLC interconnect lines are developed by using a traveling-wave-based waveform approximation (TWA) technique. The multicoupled line responses are decoupied into the eigenmodes of the system in order to exploit the TWA technique. Then, the response signals are mathematically represented by the linear combination of each eigenmode response based on TWA, followed by reporting the signal integrity models and algorithms for the multicoupled lines. The signal integrity of VLSI circuit interconnects is complicatedly correlated with input signal switching-patterns, layout geometry, and termination conditions. It is shown that the technique can be efficiently employed for complicated multicoupled interconnect lines with various termination conditions and the signal transients based on the technique have excellent agreement with SPICE simulations. Thus, with the proposed technique, the switching-dependent signal delay, crosstalk, ringing, and glitches of the inductance-effect-prominent RLC interconnect lines can be accurately as well as efficiently determined.