Analytical delay models for VLSI interconnects under ramp input
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
On switch factor based analysis of coupled RC interconnects
Proceedings of the 37th Annual Design Automation Conference
Analysis of Multiconductor Transmission Lines
Analysis of Multiconductor Transmission Lines
Impact of Deep Submicron Technology on Dependability of VLSI Circuits
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Modeling Crosstalk Induced Delay
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An analytical delay model for RLC interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Equivalent Elmore delay for RLC trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Bus energy consumption for multilevel signals
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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A new signal integrity verification method of integrated circuit interconnects with asynchronous circuit switching is presented. A ramp input is modeled with delayed step inputs. Then signal transient variations due to asynchronous input signal switching are accurately as well as efficiently determined by using Traveling-wavebased Waveform Approximation (TWA) technique. It is shown that using 90nm technology, the signal timing and crosstalk of multi-coupled lines with asynchronous switching inputs have an excellent agreement with SPICE simulation but its computation time is several thousand times faster than that of SPICE simulation using generic segment-based RLC circuit model.