Figures of merit to characterize the importance of on-chip inductance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Designing fast on-chip interconnects for deep submicrometer technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Equivalent-circuit interconnect modeling based on the fifth-order differential quadrature methods
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A clock interconnect extractor for multigigahertz frequencies incorporating inductance effect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Inductance model and analysis methodology for high-speed on-chip interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Distortion of pulsed signals in carbon nanotube interconnects
Microelectronics Journal
Complex shaped on-wafer interconnects modeling for CMOS RFICs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper investigates the properties of the on-wafer interconnects built in a 0.18- mCMOStechnology for RF applications. A scalable equivalent circuit model is developed. The model parameters are extracted directly from the on-wafer measurements and formulated into empirical expressions. The expressions are in functions of the length and the width of the interconnects. The proposed model can be easily implemented into commercial RF circuit simulators. It provides a novel solution to include the frequency-variant characteristics into a circuit simulation. The silicon-verified accuracy is proved to be up to 25 GHz with an average error less than 2%. Additionally, equivalent circuit model for longer wires can be obtained by cascading smaller subsections together. The scalability of the propose model is demonstrated.