A clock interconnect extractor for multigigahertz frequencies incorporating inductance effect

Authors:
M. A. Azadpour;T. S. Kalkur
Affiliations:
Vitesse Semiconductor Corporation, Colorado Springs, CO;Department of Electrical and Computer Engineering, University of Colorado, Colorado Springs, CO
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2003

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Abstract

Due to decreasing device sizes and increasing clock speed, interconnect inductance is becoming an important factor in the on-chip delay analysis of deep submicrometer technologies. This delay has been represented as an RC model in the available electric design automation tools. In this paper, we model the on-chip interconnect as a RLC for systems running at multigigahertz frequencies. A static-extraction analysis method optimized for ASICs is detailed. It considers all the lines within the vicinity of the target signal line as return paths.