Buffer insertion for noise and delay optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Layout techniques for minimizing on-chip interconnect self inductance
DAC '98 Proceedings of the 35th annual Design Automation Conference
A novel VLSI layout fabric for deep sub-micron applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Low-string on-chip signaling techniques: effectiveness and robustness
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Towards global routing with RLC crosstalk constraints
Proceedings of the 39th annual Design Automation Conference
Post global routing RLC crosstalk budgeting
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Low-power on-chip communication based on transition-aware global signaling (TAGS)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Routing of analog busses with parasitic symmetry
Proceedings of the 2005 international symposium on Physical design
A novel buffer circuit for energy efficient signaling in dual-VDD systems
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A Low-Latency and Low-Power Hybrid Insertion Methodology for Global Interconnects in VDSM Designs
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A new twisted differential line structure in global bus design
Proceedings of the 44th annual Design Automation Conference
Resource based optimization for simultaneous shield and repeater insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Extended global routing with RLC crosstalk constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient shield insertion for inductive noise reduction in nanometer technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A clock interconnect extractor for multigigahertz frequencies incorporating inductance effect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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Many physical synthesis tools interdigitate signal and power lines to reduce cross-talk, and thus, improve signal integrity and timing predictability. Such approaches are extremely effective at reducing cross-talk at circuit speeds where inductive effects are inconsequential. In this paper, we use a detailed distributed RLC model to show that inductive cross-talk effects are substantial in long busses associated with 0.18 micron technology. Simulation experiments are then used to demonstrate that cross-talk in such high speed technologies is much better controlled by re-deploying interdigitated power lines to perform differential signaling.