Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Low-string on-chip signaling techniques: effectiveness and robustness
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Modeling and analysis of differential signaling for minimizing inductive cross-talk
Proceedings of the 38th annual Design Automation Conference
Repeater and current-sensing hybrid circuits for on-chip interconnects
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Current Sensing Techniques for Global Interconnects in Very Deep Submicron(VDSM) CMOS
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A Low-Swing Differential Signaling Scheme for On-Chip Global Interconnects
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
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Current VLSI designs face a serious performance bottleneck due to reverse scaling of global interconnects as CMOS technology scales into VDSM regime. Interconnections techniques which decrease delay, power, and ensure signal integrity, play an important role in the growth of semiconductor industry into future generations. In this paper we present a novel hybrid insertion methodology for on-chip global interconnects. It takes advantage of repeaters and low-swing differential-signaling transceivers on driving long wires in different length, and optimally inserts them along the wires in order to decrease delay, power and gate area cost of interconnects. Simulation results using HSPICE for 0.18ìm process showed that delay, power, delay-energy-product (EDP) and gate area cost were considerably decreased compared with other approaches available. Moreover, its computational technique is relatively easy and not limited to a specific low-swing differential-signaling transceiver. Therefore the methodology is very suitable for integration in EDA tool flow and beneficial for the reuse of low-swing differential-signaling transceivers.