Optimal wire sizing and buffer insertion for low power and a generalized delay model
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Optimal wiresizing under the distributed Elmore delay model
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Wire segmenting for improved buffer insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
Interconnect design for deep submicron ICs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Minimization of chip size and power consumption of high-speed VLSI buffers
Proceedings of the 1997 international symposium on Physical design
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Buffer block planning for interconnect planning and prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Low Power Digital CMOS Design
Design and selection of buffers for minimum power-delay product
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Practical repeater insertion for low power: what repeater library do we need?
Proceedings of the 41st annual Design Automation Conference
An efficient surface-based low-power buffer insertion algorithm
Proceedings of the 2005 international symposium on Physical design
A sensitivity analysis of low-power repeater insertion
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
A Low-Latency and Low-Power Hybrid Insertion Methodology for Global Interconnects in VDSM Designs
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
POMR: a power-aware interconnect optimization methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 0.00 |
This paper studies the problems of minimizing power dissipationof an interconnect wire by simultaneously considering buffer insertion/sizing and wire sizing (BISWS). We consider two cases, namely minimizing power dissipation with optimal delay constraints, and minimizing power dissipation with a given delay penalty.We derive closed form optimal solutions for both cases. Theseclosed form solutions can be used to efficiently estimate the powerdissipation in the early stages of the VLSI designs. We observe thatthe power dissipation can be much different even with the sameoptimal delay.