Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
A module generator for optimized CMOS buffers
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
iCOACH: a circuit optimization aid for CMOS high-performance circuits
Integration, the VLSI Journal
Explicit evaluation of short circuit power dissipation for CMOS logic structures
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Introduction to VLSI Systems
Formal sizing rules of CMOS circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Internal power modelling and minimization in CMOS inverters
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
An efficient low-power buffer insertion with time and area constraints
ICC'10 Proceedings of the 14th WSEAS international conference on Circuits
POMR: a power-aware interconnect optimization methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Using explicit modeling of delays, we present and discuss real design conditions of CMOS buffers from the viewpoint of power dissipation. Efficiency of buffer implementation is first studied through the definition of limit for buffer insertion. Closed form alternatives to the design for minimum power-delay product are then proposed in terms of this limit. Validations are obtained through SPICE simulations on two stage inverter arrays. Applications are given to a standard cell library in comparing implementations for different selection alternatives.