Introduction to VLSI Systems
Design and selection of buffers for minimum power-delay product
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Hi-index | 0.00 |
A module generator for CMOS buffers have been written in C. The generator optimizes buffer design with respect to a user specified objective function both in terms of performance and layout. Speed, area, power consumption, power-delay, AT and AT2 are selectively optimized before the layout is produced. Such layout is generated in various configurations depending on load size. Technology file is easily updatable.