Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Wire segmenting for improved buffer insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
Closed form solution to simultaneous buffer insertion/sizing and wire sizing
Proceedings of the 1997 international symposium on Physical design
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Buffer block planning for interconnect-driven floorplanning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Proceedings of the 39th annual Design Automation Conference
Practical repeater insertion for low power: what repeater library do we need?
Proceedings of the 41st annual Design Automation Conference
Simultaneous Analytic Area and Power Optimization for Repeater Insertion
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Buffer insertion for noise and delay optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we perform the first quantitative study on the sensitivities of repeater power to available repeater width and candidate location, two key parameters of the dynamic programming (DP) based repeater insertion algorithms. Based on our analysis, we propose a simple yet effective scheme to select repeater widths and locations for DP-based algorithms, achieving an excellent trade-off between the solution quality and runtime. Experimental results have shown that, when combined with our sensitivity-guided scheme, the DP algorithm can attain more than 6 times speedup with negligible power degradation.