DAC '98 Proceedings of the 35th annual Design Automation Conference
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Buffer block planning for interconnect-driven floorplanning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2001 international workshop on System-level interconnect prediction
Statistically Aware Buffer Planning
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Practical repeater insertion for low power: what repeater library do we need?
Proceedings of the 41st annual Design Automation Conference
RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A sensitivity analysis of low-power repeater insertion
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Proceedings of the 42nd annual Design Automation Conference
Low-power repeater insertion with both delay and slew rate constraints
Proceedings of the 43rd annual Design Automation Conference
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Design and optimization of on-chip interconnects using wave-pipelined multiplexed routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A global interconnect link design for many-core microprocessors
IFMT '08 Proceedings of the 1st international forum on Next-generation multicore/manycore technologies
A power-efficient multipin ILP-based routing technique
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Variability aware low-power delay optimal buffer insertion for global interconnects
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2009 IEEE system-on-chip conference
POMR: a power-aware interconnect optimization methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present an analytic formula for repeater insertion in globalinterconnects that simultaneously minimizes silicon device areaand power dissipation for a given performance 驴{crit}/K where 驴{crit}is the minimum possible delay along a global interconnect, withrepeaters inserted, and 0