Reliable non-zero skew clock trees using wire width optimization
DAC '93 Proceedings of the 30th international Design Automation Conference
Process variation aware clock tree routing
Proceedings of the 2003 international symposium on Physical design
Simultaneous Analytic Area and Power Optimization for Repeater Insertion
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Variability-Driven Buffer Insertion Considering Correlations
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
An O(mn) time algorithm for optimal buffer insertion of nets with m sinks
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Process variation robust clock tree routing
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast min-cost buffer insertion under process variations
Proceedings of the 44th annual Design Automation Conference
Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hi-index | 0.00 |
Global interconnect delay variations may cause clock skew, unpredictable signal line delays, and degraded system performance. Conventional variation mitigation techniques incur large delay and power overheads, as variability increases in sub-65 nm technologies. This paper presents a methodology to include robustness optimization in power-delay optimal buffer insertion. Closed form expressions are derived for the delay variation model used in the optimization and its accuracy is verified against simulation results. Using the power, delay, and delay variation models, a design space is constructed for the interconnect. Through power-robustness trade-off analysis of the design space, the optimal buffering solution for the interconnect is computed. Comparison with simulation results verifies the accuracy of the optimal solution computed using this method. The application of this methodology in enhancing robustness of clock networks during buffer insertion phase is demonstrated and simulation results presented.