IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Statistical timing for parametric yield prediction of digital integrated circuits
Proceedings of the 40th annual Design Automation Conference
Design and reliability challenges in nanometer technologies
Proceedings of the 41st annual Design Automation Conference
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2004 international symposium on Low power electronics and design
The care and feeding of your statistical static timer
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Process and environmental variation impacts on ASIC timing
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Analysis of on-chip inductance effects for distributed RLC interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Thermal-aware methodology for repeater insertion in low-power VLSI circuits
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Thermal-aware task scheduling at the system software level
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Thermal-aware methodology for repeater insertion in low-power VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A power-efficient multipin ILP-based routing technique
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Variability aware low-power delay optimal buffer insertion for global interconnects
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2009 IEEE system-on-chip conference
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This paper addresses the problem of power dissipation during the buffer insertion phase of interconnect performance optimization in nanometer scale designs taking all significant parameter variations into account. The relative effect of different device, interconnect and environmental variations on delay and different components of power has been studied. A probabilistic framework to optimize buffer-interconnect designs under variations has been presented and results are compared with those obtained through simple deterministic optimization. Also, statistical models for delay and power under parameter variations have been developed using linear regression techniques. Under statistical analysis, both power and performance of buffer-interconnect designs are shown to degrade with increasing amount of variations. Also, % error in power estimation for power-optimal repeater designs is shown to be significant if variations are not taken into account. Furthermore, it has been shown that due to variations, significantly higher penalties in delay are needed to operate at power levels similar to those under no variations. Finally, the percentage savings in total power for a given penalty in delay are shown to improve with increasing amount of parameter variations.