CMOS system-on-a-chip voltage scaling beyond 50nm
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
TACO: timing analysis with coupling
Proceedings of the 37th Annual Design Automation Conference
Modeling and forecasting of manufacturing variations (embedded tutorial)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Test structures for delay variability
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Timing Analysis in Presence of Power Supply and Ground Voltage Variations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 42nd annual Design Automation Conference
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Testing On-Die Process Variation in Nanometer VLSI
IEEE Design & Test
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
The Predictive Technology Model in the Late Silicon Era and Beyond
Foundations and Trends in Electronic Design Automation
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The integrated circuit fabrication process has inevitable imperfections and fluctuations that had resulted in ever-growing systematic and random variations in the electrical parameters of active and passive devices fabricated as stated in S. Nassif (2001). The impact of such variations on various aspects of chip performance has been the subject of numerous recent papers, and techniques for analyzing and dealing with such variability roadly labeled design for manufacturability (DFM) - are emerging from research laboratories to practical implementation and deployment, and several service companies are actively engaged in implementing and promoting DFM techniques amongst semiconductor design and manufacturing organizations.