Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Statistical Modeling for Circuit Simulation
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Design For Degradation: CAD Tools for Managing Transistor Degradation Mechanisms
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
The care and feeding of your statistical static timer
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Modeling and minimization of PMOS NBTI effect for robust nanometer design
Proceedings of the 43rd annual Design Automation Conference
Predictive technology model for nano-CMOS design exploration
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Carbon nanotube transistor circuits: models and tools for design and performance optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A Test-Structure to Efficiently Study Threshold-Voltage Variation in Large MOSFET Arrays
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Fast statistical circuit analysis with finite-point based transistor model
Proceedings of the conference on Design, automation and test in Europe
The impact of NBTI on the performance of combinational and sequential circuits
Proceedings of the 44th annual Design Automation Conference
Compact modeling of carbon nanotube transistor for early stage process-design exploration
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Single-walled carbon nanotube electronics
IEEE Transactions on Nanotechnology
Analysis of the Frequency Response of Carbon Nanotube Transistors
IEEE Transactions on Nanotechnology
A circuit-compatible model of ballistic carbon nanotube field-effect transistors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The aggressive scaling of CMOS technology has inevitably led to vastly increased power dissipation, process variability and reliability degradation, posing tremendous challenges to robust circuit design. To continue the success of integrated circuits, advanced design research must start in parallel with or even ahead of technology development. This new paradigm requires the Predictive Technology Model (PTM) for future technology generations, including nanoscale CMOS and post-silicon devices. This paper presents a comprehensive set of predictive modeling developments. Starting from the PTM of traditional CMOS devices, it extends to CMOS alternatives at the end of the silicon roadmap, such as strained Si, high-k/metal gate, and FinFET devices. The impact of process variation and the aging effect is further captured by modeling the device parameters under the influence. Beyond the silicon roadmap, the PTM outreaches to revolutionary devices, especially carbon-based transistor and interconnect, in order to support explorative design research. Overall, these predictive device models enable early stage design exploration with increasing technology diversity, helping shed light on the opportunities and challenges in the nanoelectronics era.