Proceedings of the 13th international symposium on Low power electronics and design
The Predictive Technology Model in the Late Silicon Era and Beyond
Foundations and Trends in Electronic Design Automation
IEEE Transactions on Circuits and Systems Part I: Regular Papers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A test-structure comprising a dual-slope integrating analog-to-digital converter, auto-zeroing circuitry, digital control logic and a large array of Devices Under Test (DUTs) has been developed to isolate threshold voltage variation.. Threshold-voltage (VT) isolation is achieved by testing all DUTs in the subthreshold regime where drain-to-source current is an exponential function of VT. Spice simulations show that the structure is at least an order of magnitude more sensitive to VT variation than to channel length variation. This, in combination with a hierarchical access scheme and leakage control system, allows efficient characterization of ..VT for ~70,000 NMOS and ~70,000 PMOS devices in a dense 2mm x 2mm DUT array.