Transistor variability modeling and its validation with ring-oscillation frequencies for body-biased subthreshold circuits

Authors:
Hiroshi Fuketa;Masanori Hashimoto;Yukio Mitsuyama;Takao Onoye
Affiliations:
Department of Information Systems Engineering, Osaka University, Osaka, Japan and JST, CREST, Tokyo, Japan;Department of Information Systems Engineering, Osaka University, Osaka, Japan and JST, CREST, Tokyo, Japan;Department of Information Systems Engineering, Osaka University, Osaka, Japan and JST, CREST, Tokyo, Japan;Department of Information Systems Engineering, Osaka University, Osaka, Japan and JST, CREST, Tokyo, Japan
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2010

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Abstract

This paper presents transistor variability modeling and its validation for body-biased subthreshold circuits based on measurements of a device-array circuit using a 90-nm technology. The device array consists of p/nMOS transistors and ring oscillators. We examine and confirm the correlation between the performance variation model extracted from measured I-V characteristics and fabricated oscillation frequencies. We demonstrate that delay variations in subthreshold circuits are well characterized with two parameters, i.e., threshold voltage and subthreshold swing parameter. We also reveal that threshold voltage shift by body biasing can be deterministically modeled and statistical modeling is less meaningful.