Theoretical and practical limits of dynamic voltage scaling
Proceedings of the 41st annual Design Automation Conference
Characterizing and modeling minimum energy operation for subthreshold circuits
Proceedings of the 2004 international symposium on Low power electronics and design
Power-optimal pipelining in deep submicron technology
Proceedings of the 2004 international symposium on Low power electronics and design
Energy Optimization of Subthreshold-Voltage Sensor Network Processors
Proceedings of the 32nd annual international symposium on Computer Architecture
Ultra-low-power DLMS adaptive filter for hearing aid applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The limit of dynamic voltage scaling and insomniac dynamic voltage scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variation-driven device sizing for minimum energy sub-threshold circuits
Proceedings of the 2006 international symposium on Low power electronics and design
Proceedings of the 2006 international symposium on Low power electronics and design
Utilizing reverse short channel effect for optimal subthreshold circuit design
Proceedings of the 2006 international symposium on Low power electronics and design
Energy optimality and variability in subthreshold design
Proceedings of the 2006 international symposium on Low power electronics and design
Ultralow-voltage, minimum-energy CMOS
IBM Journal of Research and Development - Advanced silicon technology
Analyzing and modeling process balance for sub-threshold circuit design
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Energy efficient near-threshold chip multi-processing
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Vt balancing and device sizing towards high yield of sub-threshold static logic gates
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Variations-aware low-power design and block clustering with voltage scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Utilizing reverse short-channel effect for optimal subthreshold circuit design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimal technology selection for minimizing energy and variability in low voltage applications
Proceedings of the 13th international symposium on Low power electronics and design
Variability of flip-flop timing at sub-threshold voltages
Proceedings of the 13th international symposium on Low power electronics and design
Analog Integrated Circuits and Signal Processing
Subthreshold FIR Filter Architecture for Ultra Low Power Applications
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Reconfigurable energy efficient near threshold cache architectures
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Slew-aware clock tree design for reliable subthreshold circuits
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Interests and limitations of technology scaling for subthreshold logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-efficient subthreshold processor design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Clock network design for ultra-low power applications
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Timing modeling for digital sub-threshold circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Variation resilient adaptive controller for subthreshold circuits
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Regular fabric for regular FPGA (abstract only)
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Variation-aware clock network design methodology for ultra-low voltage (ULV) circuits
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Near-/sub-threshold DLL-based clock generator with PVT-aware locking range compensation
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design
Proceedings of the 48th Design Automation Conference
Ultra-low-power signaling challenges for subthreshold global interconnects
Integration, the VLSI Journal
Standard cell sizing for subthreshold operation
Proceedings of the 49th Annual Design Automation Conference
Process variation in near-threshold wide SIMD architectures
Proceedings of the 49th Annual Design Automation Conference
Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology
Design of energy-efficient, adaptable throughput systems at near/sub-threshold voltage
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Full-Swing Gate Diffusion Input logic-Case-study of low-power CLA adder design
Integration, the VLSI Journal
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Subthreshold circuit design is a compelling method for ultra-low power applications. However, subthreshold designs show dramatically increased sensitivity to process variations due to the exponential relationship of subthreshold drive current with V th variation. In this paper, we present an analysis of subthreshold energy efficiency considering process variation, and propose methods to mitigate its impact. We show that, unlike superthreshold circuits, random dopant fluctuation is the dominant component of variation in subthreshold operation. We investigate how this variability can be ameliorated with proper circuit sizing and choice of circuit logic depth. We then present a statistical analysis of the energy efficiency of subthreshold circuits considering process variations. We show that the energy optimal supply voltage increases due to process variations and study its dependence on circuit parameters. We verify our analytical models against Monte Carlo SPICE simulations and show that they accurately predict the minimum energy and energy optimal supply voltage. Finally, we use the developed statistical energy model to determine the optimal pipelining depth in subthreshold designs