Analysis and mitigation of variability in subthreshold design
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing
Proceedings of the 43rd annual Design Automation Conference
Variation-driven device sizing for minimum energy sub-threshold circuits
Proceedings of the 2006 international symposium on Low power electronics and design
Utilizing reverse short channel effect for optimal subthreshold circuit design
Proceedings of the 2006 international symposium on Low power electronics and design
Timing modeling for digital sub-threshold circuits
Proceedings of the Conference on Design, Automation and Test in Europe
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Process variability severely impacts the performance of circuits operating in the subthreshold domain. Among other reasons, this mainly stems from the fact that subthreshold current follows a widely spread Log-Normal distribution. In this paper we introduce a new transistor sizing methodology for standard cells. Our premise relies on balancing the N and P network currents based on statistical formulations. Our approach renders more robust cells. We observe up to 57% better performance and 69% lower energy consumption on a set of ISCAS circuits when they are synthesized with our library as opposed to a commercial library in a CMOS 90nm technology.