Novel sizing algorithm for yield improvement under process variation in nanometer technology
Proceedings of the 41st annual Design Automation Conference
Theoretical and practical limits of dynamic voltage scaling
Proceedings of the 41st annual Design Automation Conference
Characterizing and modeling minimum energy operation for subthreshold circuits
Proceedings of the 2004 international symposium on Low power electronics and design
Proceedings of the 42nd annual Design Automation Conference
A variation tolerant subthreshold design approach
Proceedings of the 42nd annual Design Automation Conference
Analysis and mitigation of variability in subthreshold design
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Energy optimality and variability in subthreshold design
Proceedings of the 2006 international symposium on Low power electronics and design
Analyzing and modeling process balance for sub-threshold circuit design
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Vt balancing and device sizing towards high yield of sub-threshold static logic gates
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Statistical noise margin estimation for sub-threshold combinational circuits
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Optimal technology selection for minimizing energy and variability in low voltage applications
Proceedings of the 13th international symposium on Low power electronics and design
Proceedings of the 13th international symposium on Low power electronics and design
Variability of flip-flop timing at sub-threshold voltages
Proceedings of the 13th international symposium on Low power electronics and design
Subthreshold FIR Filter Architecture for Ultra Low Power Applications
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Slew-aware clock tree design for reliable subthreshold circuits
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Interests and limitations of technology scaling for subthreshold logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-efficient subthreshold processor design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timing modeling for digital sub-threshold circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Variation resilient adaptive controller for subthreshold circuits
Proceedings of the Conference on Design, Automation and Test in Europe
The impact of inverse narrow width effect on sub-threshold device sizing
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Energy dissipation reduction of a cardiac event detector in the Sub-Vt
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Ultra-low-power signaling challenges for subthreshold global interconnects
Integration, the VLSI Journal
Limit study of energy & delay benefits of component-specific routing
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Standard cell sizing for subthreshold operation
Proceedings of the 49th Annual Design Automation Conference
A fine-grained many VT design methodology for ultra low voltage operations
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Sub-threshold operation is a compelling approach for energy-constrained applications, but increased sensitivity to variation must be mitigated. We explore variability metrics and the variation sensitivity of stacked device topologies. We show that upsizing is necessary to achieve robustness at reduced voltages and propose a design methodology to meet yield constraints. The need for upsizing imposes an energy overhead, influencing the optimal supply voltage to minimize energy. Finally, we characterize performance variability by summing delay distributions of each stage in an arbitrary critical path and achieve results accurate to within 10% of Monte Carlo simulation.