Scaling of stack effect and its application for leakage reduction
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Theoretical and practical limits of dynamic voltage scaling
Proceedings of the 41st annual Design Automation Conference
Energy Optimization of Subthreshold-Voltage Sensor Network Processors
Proceedings of the 32nd annual international symposium on Computer Architecture
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing
Proceedings of the 43rd annual Design Automation Conference
Variation-driven device sizing for minimum energy sub-threshold circuits
Proceedings of the 2006 international symposium on Low power electronics and design
Utilizing reverse short channel effect for optimal subthreshold circuit design
Proceedings of the 2006 international symposium on Low power electronics and design
Analysis and optimization of sleep modes in subthreshold circuit design
Proceedings of the 44th annual Design Automation Conference
Nanometer device scaling in subthreshold circuits
Proceedings of the 44th annual Design Automation Conference
Optimal technology selection for minimizing energy and variability in low voltage applications
Proceedings of the 13th international symposium on Low power electronics and design
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Efficient statistical leakage analysis using deterministic cell leakage models
Microelectronics Journal
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This paper investigates the optimization of sleep mode energy consumption for ultra-low Vdd CMOS circuits, which is motivated by our findings that minimization of sleep mode energy holds great potential for reducing total energy consumption. We propose a unique approach of using a power gating switch (PGS) in ultra-low Vdd regimes. Unlike the conventional manner of using PGSs, our optimization suggests using minimal-sized PGSs with a slightly higher Vdd to compensate for voltage drop across the PGS. In SPICE simulations, this reduces total energy consumption by ∼125× compared to conventional approaches. The effectiveness of the proposed optimization is also confirmed by measurements taken from an ultra-low power microprocessor. Additionally, the feasibility of using minimal PGSs in ultra-low Vdd regimes is investigated using SPICE simulations and silicon measurements.