Design and optimization of dual-threshold circuits for low-voltage low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and mitigation of variability in subthreshold design
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Variation-driven device sizing for minimum energy sub-threshold circuits
Proceedings of the 2006 international symposium on Low power electronics and design
Optimal technology selection for minimizing energy and variability in low voltage applications
Proceedings of the 13th international symposium on Low power electronics and design
Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Interests and limitations of technology scaling for subthreshold logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical Timing Analysis: From Basic Principles to State of the Art
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Clock network design for ultra-low power applications
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Automatic synthesis of near-threshold circuits with fine-grained performance tunability
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Row-based FBB: A design-time optimization for post-silicon tunable circuits
Microelectronics Journal
Decoupling capacitor design strategy for minimizing supply noise of ultra low voltage circuits
Proceedings of the 49th Annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improving platform energy: chip area trade-off in near-threshold computing environment
Proceedings of the International Conference on Computer-Aided Design
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We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show that technology flavor and Vt selections shift minimum-energy point to different operating frequencies, thereby enabling minimum energy in either low- or mid-performance applications. However, we demonstrate that independent dual-Vt assignment to save leakage in non-critical paths is not feasible. We then show that reverse adaptive body biasing (ABB) is potentially more efficient to compensate for global process/temperature variations than adaptive voltage scaling and forward ABB. Nevertheless, its practical efficiency is limited by the affordable VBB range and the value of the body-effect coefficient.