Proceedings of the 2003 international symposium on Low power electronics and design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
An efficient algorithm for statistical minimization of total power under timing yield constraints
Proceedings of the 42nd annual Design Automation Conference
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Introduction to Operations Research and Revised CD-ROM 8
Introduction to Operations Research and Revised CD-ROM 8
Active mode leakage reduction using fine-grained forward body biasing strategy
Integration, the VLSI Journal
Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
Temperature-adaptive voltage tuning for enhanced energy efficiency in ultra-low-voltage circuits
Microelectronics Journal
Adaptive techniques for overcoming performance degradation due to aging in digital circuits
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A new compensation mechanism for environmental parameter fluctuations in CMOS digital ICs
Microelectronics Journal
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Circuit techniques for dynamic variation tolerance
Proceedings of the 46th Annual Design Automation Conference
Post-manufacture tuning for nano-CMOS yield recovery using reconfigurable logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Body bias voltage computations for process and temperature compensation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Circuit variability has adverse consequences on design predictability and yield in Nanometer CMOS. Post-fabrication tuning approaches have been targeted in a number of recent works to mitigate this problem. Adaptive Body Bias (ABB) is one of the most successful tuning knobs in use today in high-performance custom design. Through forward body bias (FBB), the threshold voltage of the CMOS devices can be reduced after fabrication to bring the slow dies back within the range of acceptable specs. FBB is usually applied with a very coarse granularity at the price of a significantly increased leakage power. We propose a novel, fine-grained FBB scheme on row-based standard cell layout that enables selective forward body biasing of those rows that contain most timing critical gates, thereby reducing leakage power overhead. This style is fully compatible with state-of-the-art commercial physical design flows and imposes minimal area blow-up. It can be applied without any placement disruption on a fully placed design. Benchmark results show large leakage power savings with a maximum savings of 61% in case of 18% compensation in 45nm and 93% in case of 10% compensation in 32nm with respect to block-level approaches.