Active mode leakage reduction using fine-grained forward body biasing strategy

Authors:
Vishal Khandelwal;Ankur Srivastava
Affiliations:
Department of Electrical and Computer Engineering, University of Maryland, College Park, USA;Department of Electrical and Computer Engineering, University of Maryland, College Park, USA
Venue:
Integration, the VLSI Journal
Year:
2007

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Abstract

Leakage power minimization has become an important issue with technology scaling. Variable threshold voltage schemes have become popular for standby power reduction. In this work we look at another emerging aspect of this potent problem which is leakage power reduction in active mode of operation. In gate level circuits, a large number of gates are not switching in active mode at any given point in time but nevertheless are consuming leakage power. We propose a fine-grained forward body biasing (FBB) scheme for active mode leakage power reduction in gate level circuits without any delay penalty. Our results show that our optimal polynomial time FBB allocation algorithm results in 70.2% reduction in leakage currents. We also present an exact standard-cell placement driven FBB allocation algorithm that effectively reduces the area penalty using the post-placement area slack and results in 56.5%, 62.8% and 66.1% reduction in leakage currents for 0%, 4% and 8% area slack, respectively. Furthermore, we present a heuristic to solve the standard-cell placement driven FBB allocation problem that is computationally efficient and results in leakage within 2% of that from the exact formulation.